The topology of a high-speed multiplexer (MUX) implemented with true single-phase clock/clocked/clocking (TSPC) logic can be prone to glitches or errors at lower clock rates. While TSPC logic is a dynamic logic family intended for high-speed operation, it is often advantageous to run TSPC circuits at lower frequencies. For the TSPC MUX, charges can be transferred between two floating nodes on the circuit. This charge transfer can, for example, reduce the voltage of a node that should remain in a logic high state. With a slightly lower voltage on this node, a subsequent transistor can turn on weakly and pull the voltage high of a subsequent node that should remain low. This can cause a glitch at the output of the circuit.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those in light of the present disclosure.